1. Field of the Invention
This invention generally relates to phase locked-loops and, more particularly, to a duty-cycle feedback charge pump suitable for use in delay locked-loops (DLLs) and phase locked-loops (PLLs).
2. Description of the Related Art
A charge pumps is often interposed between the phase detector and voltage controlled oscillator (VCO) of a PLL to condition the VCO control voltage. In a PLL the phase difference between the reference signal and the output signal is translated into two opposite voltage polarities, or in the case of differential signals—UP and DN. The two signals control switches to steer current into or out of a capacitor, causing the voltage across the capacitor to increase or decrease. In each cycle, the time during which the switch is turned on is proportional to the phase difference. Hence, the charge delivered is dependent on the phase difference. The voltage on the capacitor is used to tune the VCO, generating the desired output signal frequency.
FIG. 2 is a schematic diagram of a charge pump, as presented by Gersbach et al., U.S. Pat. No. 5,508,660, entitled, Charge pump circuit with symmetrical current output for phase-controlled loop system (prior art). The depicted design is not a low-voltage solution, and the use of a voltage signal as feedback imposes supply limitations, resulting is a complex, high-cost design. For example, separate up/down signals are required, so a differential output phase detector is needed. Further, the design has stability challenges, and only capable of Class B operation in a feedback loop.
Bereza et al., in U.S. Pat. No. 5,801,578, entitled, Charge pump circuit with source-sink current steering present a design that is not a low-voltage solution, and the use of voltage signal as feedback imposes supply limitations. The open-loop control of current-matching is not robust, and there is a need for separate up/down signals, requiring a more complex phase detector.
FIG. 3 is a schematic diagram of a charge pump as presented by Sudjian et al., U.S. Pat. No. 7,015,736, entitled, Symmetric Charge pump (prior art). Again, the design is not a low-voltage solution. The use of a voltage signal as feedback imposes supply design limitations. There is need for a differential output phase detector, and the open-loop control of current matching is not robust.
FIG. 4 is a schematic diagram of the DLL of FIG. 1, showing the charge pump in greater detail. After each half-period:
      V          C      ⁡              (        new        )              =                    V                  C          ⁡                      (            old            )                              -                                    t            ON                    ⁢                      I            N                          C            +                                    t            OFF                    ⁢                      I            P                          C              =                            V                      C            ⁡                          (              old              )                                      -                                            t              ON                        ⁢                          I              N                                C                +                                                            (                                                      T                    /                    2                                    -                                      t                    ON                                                  )                            ⁢                              I                P                                      C                    ⁢                      t            ON                              =              4        ⁢                                  ⁢                  Tdelay          ⁡                      (                          V              C                        )                              
After the DLL loop is settled:
      V          C      ⁡              (        new        )              =            V              C        ⁡                  (          old          )                      -                            t          ON                ⁢                  I          N                    C        +                                        (                                          T                /                2                            -                              t                ON                                      )                    ⁢                      I            p                          C            .      
  {                                                        t              ON                        =                                          (                                  T                  /                  2                                )                            ⁢                                                I                  P                                                                      I                    N                                    +                                      I                    P                                                                                                                                      t              OFF                        =                                          (                                  T                  /                  2                                )                            ⁢                                                I                  N                                                                      I                    N                                    +                                      I                    P                                                                                            ⁢    and  
To have the signals at the input of the XOR (PD) orthogonal (90° out of phase), and hence accurately settling on the desired delay, tON should be equal to tOFF, assuming that clock has a 50% duty-cycle.IP=IN 
For best delay accuracy Ip should be kept equal to In in all process/voltage/temperature (PVT) corners, which is especially challenging when using supply voltages as low as 0.67 V. Complex phase detectors and charge pumps have been used to address this problem.
FIG. 6 is a schematic diagram of a charge pump with no current matching (prior art). Advantageously, the design is simple and self-biased. However, the design is dependent upon the supply voltages, and mismatches between the PMOS and NMOS transistors result in delay offsets after the loop has locked and is settled. It is difficult to precisely match the Ip and In currents, especially at low supply voltages.
FIGS. 7A and 7B are schematic and signal graphs, respectively, of a charge pump with open-loop current matching (prior art). Advantageously, the design is simple, self-biased, and has better current matching than the design of FIG. 6. However, the matching is coarse. Mismatch between PMOS and NMOS current occur due to different drain-source voltages (VDS) and regions of operation. As seen in FIG. 7B, an unbalanced (non-50%) duty cycle at the input of the charge pump causes steady state errors in the overall loop.
The design is also very dependent on V(OUT), which has a wide range of variation. Further, mismatch in PMOS and NMOS current results in delay offsets after locking and settling, and as mentioned above, it is difficult to match Ip to In at low voltages.
It would be advantageous if a charge pump design could effectively match Ip to In currents when using relatively low control voltages.